Computer Engineering

Advika Metre

MS Computer Engineering student at NC State University, specializing in

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Passionate about building efficient hardware from the ground up.

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Technical Projects
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BTech CGPA
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LUT Reduction
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National Debate Finals

Education

North Carolina State University

Master of Science (MS), Computer Engineering

2025 โ€“ 2027

Coursework

Architecture of Parallel ComputersASIC and FPGA Design with VerilogMicroprocessor Architecture

Upcoming Courses

ASIC Verification using System VerilogAdvanced Microarchitecture

Shri Ramdeobaba College of Engineering and Management

Nagpur, India

Bachelor of Technology (BTech), Electronics Engineering

2021 โ€“ 2025CGPA: 9.42

Work Experience

Research Intern โ€” Memory Built-In Self-Test

Electronics Department, RCOEM

Nov 2024 โ€“ May 2025
  • Designed and implemented Verilog FSM BIST for March C- and Checkerboard on Xilinx Artix-7, with built-in fault injection; added a parallel hybrid flow using dual-port BRAM to increase test throughput.
  • Reduced the LUT count by 22% and the power consumption while effectively addressing limitations in detecting complex in-transition and stuck-at faults.

Summer Intern โ€” Ecostruxure Development

VNIT

June 2024 โ€“ July 2024
  • Configured Schneider Ecostruxure IIoT panels with AR-enabled devices to stream equipment telemetry for remote diagnostics and faster issue resolution.
  • Used SoMove, Augmented Operator Advisor, Machine Expert, and Secure Connect to program, integrate, and troubleshoot deployed systems.

Projects

CNN Accelerator with DRAM Interface

RTL DesignVerilog

Complete CNN inference pipeline streaming directly from DRAM with custom memory controller.

Click to expand details โ†’

Superscalar Pipeline Simulator

CPU ArchitectureC++

Configurable out-of-order superscalar CPU simulator with full pipeline modeling.

Click to expand details โ†’

Bus Based Cache Coherence Protocols

Multi-core SystemsMemory ConsistencyC++

Adaptive MOESI coherence variant evaluated on 16-core SMP simulations.

Click to expand details โ†’

Cache and Memory Hierarchy Simulator

CPU ArchitectureC++OOP

Flexible L1/L2 cache simulator with WBWA policy, LRU replacement, and stream buffers.

Click to expand details โ†’

Skills

Languages

CC++PythonVerilogSystem VerilogCUDA

Tools & Platforms

VivadoLinuxModelsimLTSpice

Concepts

RTL DesignComputer ArchitectureDigital DesignCache CoherenceStatic Timing Analysis

Blog

Achievements

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IEEE Conference Paper

"FSM Based Implementation of March C- and Checkerboard Algorithm", presented at IEEE 6th International Conference for Emerging Technology (INCET), Belagavi, India, 2025.

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National Debating Finalist

3ร— National Debating Finalist โ€” IIT Madras, IIM Indore, VNIT โ€” 2024, 2023, 2022.