Technical deep dives on computer architecture, RTL design, and hardware engineering.
A deep dive into how modern multi-core processors keep their caches consistent, exploring the tradeoffs between MOESI and MESI protocols and when adaptive approaches shine.
What I learned building a complete CNN inference pipeline in Verilog — from DRAM interfacing to timing closure, and why hardware design forces you to think differently.
How I built a configurable superscalar CPU simulator in C++ to explore the design space of modern processors — and what the bottleneck analysis revealed.
The journey of implementing March C- and Checkerboard BIST algorithms as synthesizable Verilog FSMs on a Xilinx Artix-7 FPGA.