FSM-Based Memory BIST: From Algorithm to Silicon

What is Memory BIST?

Built-In Self-Test (BIST) for memories embeds test logic directly on-chip, allowing memories to test themselves without external equipment. This is critical for:

• Manufacturing test: Detecting defects before shipping
• In-field test: Periodic health checks in safety-critical systems
• Yield analysis: Characterizing failure modes across wafers

The Algorithms

March C-

March C- is a well-known march test that detects stuck-at faults, transition faults, and coupling faults. It consists of six march elements:

1. ⇑ (w0) — Write 0 to all addresses in ascending order
2. ⇑ (r0, w1) — Read 0, write 1, ascending
3. ⇑ (r1, w0) — Read 1, write 0, ascending
4. ⇓ (r0, w1) — Read 0, write 1, descending
5. ⇓ (r1, w0) — Read 1, write 0, descending
6. ⇑ (r0) — Read 0, ascending (verification)

Checkerboard

Checkerboard writes an alternating 0/1 pattern (like a chessboard) and its complement, checking for pattern-sensitive faults that March C- might miss.

FSM Implementation

The core of the BIST controller is a finite state machine with states for each march element. Key design choices:

• Parameterized address width and data width for reuse across different memory sizes
• Built-in fault injection via a configuration register that can flip specific bits during write operations — essential for validating that the BIST actually catches faults
• Pass/fail status register accessible via a simple scan interface

The Parallel Hybrid Flow

The standard serial approach — run March C-, then Checkerboard — wastes time. I implemented a parallel hybrid using dual-port BRAM:

• Port A runs March C- on the upper half of memory
• Port B runs Checkerboard on the lower half
• After completion, they swap and repeat

This effectively doubled test throughput with minimal area overhead (the dual-port BRAM was already available on the Artix-7).

Results

• LUT reduction: 22% fewer LUTs compared to a naive implementation, achieved by sharing the address generator and comparator logic between march elements
• Fault coverage: Successfully detected stuck-at-0, stuck-at-1, transition, and address-decoder faults in simulation
• Power: The FSM approach consumes less dynamic power than a microcode-based BIST because there's no instruction fetch/decode overhead

This work was presented at IEEE INCET 2025 in Belagavi, India.